| Processor Core |
64 – bit dual – issue superscalar LA264, supports LoongArch instruction set |
| Main Frequency |
1GHz |
| High – speed Cache |
32KB L1 instruction cache and 32KB L1 data cache, supports ECC verification; 512KB L2 shared cache, supports ECC verification |
| Memory Controller |
16 – bit DDR4 – 1600 controller, supports ECC verification |
| High – speed I/O |
2 USB2.0, 2 GMAC, 1 – channel LCD display |
| Package |
12mm×12mm FC – CSP package, 286 pins |
| Power Management |
Supports dynamic frequency scaling of processor core clock; Supports dynamic clock gating of main modules |
| Typical Power Consumption |
<1W@1GHz |
| Other I/O (1) |
1 I2S, 4 CAN – FD, 4 SPI, 2 QSPI, 2 eMMC, 2 SDIO, 1 LIO, 8 – channel ADC, 4 I2C, 10 UART |
| Other I/O (2) |
4 PWM, 3 sets of TIMER, 106 GPIO, RTC, HPET, JTAG, etc. |
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