BCM47765 Second Generation Dual-Frequency GNSS chip

描述

Category Details
Features GNSS Subsystem
– Massively parallel search engine with separate tracking engines
– Internal LNAs with adjustable gain (noise figure <3.5 dB across PVT)
– AGPS support: GSM/UMTS/LTE (3GPP 44.031, 44.035, 25.331, 36.355)
– Excellent transmit blocker performance (single BOM filter)
– Enhanced autonomous acquisition with multi-constellation LTO data
– Synchronization pulse input for external timing
– GNSS location library API (RRLP, RRC, SUPL)
– Autonomous/MS-based/MS-assisted operation modes
– Time-stamped data buffer and sensor fusion support
Processor Arm Cortex-M4F (CM4)
– 32-bit with FPU, MPU
– 1.125 DMIPS/MHz @ 150 MHz max
– 1.125 MB SRAM (single-cycle access)
– SIMD/DSP acceleration

Arm Cortex-M0 (CM0)
– 75 MHz max, 32 KB RAM (power offload)
– 1 MB ROM (bootloader)
Interfaces High-Speed System
– SPI slave (50 MHz max)
– UART (3.2 Mb/s max)
– Peripheral DMA channels

Peripherals
– Up to 49 GPIOs
– I2S master/slave
– PDM microphone input
– 2x SPI master (50 MHz), 1x SPI slave
– 4x UART
– 1x I2C compatible (BSC)
– 12-bit, 2-channel ADC
Timers – Watchdog timer
– 42-bit RTC (32.768 kHz)
– 2x 32-bit microsecond timers
– 48-bit microsecond counter
Debug & Memory – Serial Wire Debug (SWD)
– OTP memory (wafer lot, coordinates, ATE data)
Applications – Smartphones
– Tablets
– Mobile accessories
– Wearables
– Digital cameras
Lifecycle Status Active

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