描述
| Parameter | Value |
|---|---|
| CPU | Cortex-M4F |
| CPU Speed Max MHz (megahertz) | 120 |
| Operation Voltage Max.(V) | 3.63 |
| Operation Voltage Min.(V) | 1.71 |
| Internal Oscillator | 8,16,24Mhz,32Khz,48Khz |
| Part Family | PIC32CX |
| QSPI | 1 |
| RAM KB (kilobyte) | 256 |
| Secure Subsystem | Yes |
| Program Memory size (KB) | 1024 |
| Pincount | 100 |
| Crypto Engine | Yes |
| TempRange Min. | -40 |
| TempRange Max. | 125 |
| UART | 8 |
| I2C | 8 |
| I2S | 1 |
| Category | Details |
|---|---|
| Operating Conditions (PIC32CX SG41) | 1.71V – 3.63V, -40°C to +85°C, DC to 120 MHz 1.71V – 3.63V, -40°C to +125°C, DC to 100 MHz Dual Power capable as signified by VDDIOB |
| Operating Conditions (PIC32CX SG60/SG61) | 2.7V – 3.63V, -40°C to +85°C, DC to 120 MHz 2.7V – 3.63V, -40°C to +125°C, DC to 100 MHz |
| Core | Arm® Cortex®-M4F CPU running at up to 120 MHz: – 403 CoreMark® at 120 MHz – 4 KB combined instruction cache and data cache – 8-Zone Memory Protection Unit (MPU) – Thumb®-2 instruction set – Embedded Trace Module (ETM) with instruction trace stream – CoreSight Embedded Trace Buffer (ETB) – Trace Port Interface Unit (TPIU) – Floating Point Unit (FPU) |
| Memories | 1 MB in-system self-programmable Flash with: – Error Correction Code (ECC) – Dual bank with Read-While-Write (RWW) support – EEPROM hardware emulation 256 KB SRAM main memory – 128 KB with Error Correction Code (ECC) RAM option Up to 4 KB of Tightly Coupled Memory (TCM) 8 KB additional SRAM – Can be retained in Backup mode Eight 32-bit backup registers |
| Low-Power and Power Management | Idle, Standby, Hibernate, Backup, and Off sleep modes SleepWalking peripherals Battery backup support Embedded Buck/LDO regulator supporting on-the-fly selection |
| I/O | Up to 99 programmable I/O pins |
| Security and Safety | One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate – ECB, CBC, CFB, OFB, CTR modes of operation – Supports counter with CBC-MAC mode – Galois Counter Mode (GCM) True Random Number Generator (TRNG) Public Key Cryptography Controller (PUKCC) and associated Classical Public Key Cryptography Library (PUKCL) – RSA, DSA – Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p) Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted Permanent protection against Chip Erase, Boot section Programming and Debug access, allowing Immutable Boot (optional) Size-configurable Immutable Boot section in Flash with Boot Read Protection, allowing secure boot support (optional) |
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